Scheduled System Maintenance on May 29th, 2015:
IEEE Xplore will be upgraded between 11:00 AM and 10:00 PM EDT. During this time there may be intermittent impact on performance. We apologize for any inconvenience.
By Topic

An Ultra Low-Power (⩽13.6 mW/latch) Static Frequency Divider in an InP/InGaAs DHBT Technology

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

8 Author(s)
Griffith, Z. ; Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA ; Parthasarathy, N. ; Rodwell, Mark J.W. ; Urteaga, M.
more authors

An ultra-low power static frequency divider with a maximum clock frequency > 61 GHz was designed and fabricated into a 500 nm InP/In 0.53Ga47As/InP double heterojunction bipolar transistor (DHBT) technology utilizing a collector pedestal process for reduced base-collector capacitance Ccb. This is the first reported digital circuit in this material system employing such Ccb reduction techniques. The divider operation is fully static, operating from fclk = 4 GHz to 61.2 GHz while dissipating 27.1 mW of power in the flip-flop from a single -2.30 V supply. The power-delay product of this circuit is 113.0 fJ/latch if all devices in the latch are considered and 63.2 fJ/latch if the power associated with the voltage level-shifting emitter followers is not included in the power-delay calculation. By either method of calculation, this is a record low power-delay product for an InP DHBT-based static frequency divider; more than 2times lower than has been previously reported. The circuit employs the current mode logic (CML) topology and inductive peaking

Published in:

Microwave Symposium Digest, 2006. IEEE MTT-S International

Date of Conference:

11-16 June 2006