An Ultra Low-Power (⩽13.6 mW/latch) Static Frequency Divider in an InP/InGaAs DHBT Technology

An ultra-low power static frequency divider with a maximum clock frequency > 61 GHz was designed and fabricated into a 500 nm InP/In
_0.53
Ga
₄₇
As/InP double heterojunction bipolar transistor (DHBT) technology utilizing a collector pedestal process for reduced base-collector capacitance Ccb. This is the first reported digital circuit in this material system employing such C
_cb
reduction techniques. The divider operation is fully static, operating from f
_clk
= 4 GHz to 61.2 GHz while dissipating ≤ 27.1 mW of power in the flip-flop from a single -2.30 V supply. The power-delay product of this circuit is 113.0 fJ/latch if all devices in the latch are considered, and 63.2 fJ/latch if the power associated with the voltage level-shifting emitter followers is not included in the power-delay calculation. By either method of calculation, this is a record low power-delay product for an InP DHBT-based static frequency divider; more than 2× lower than has been previously reported. The circuit employs the current mode logic (CML) topology and inductive peaking.