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A Silicon 60-GHz Receiver and Transmitter Chipset for Broadband Communications

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8 Author(s)
Scott K. Reynolds ; IBM T. J. Watson Res. Center, Yorktown Heights, NY ; Brian A. Floyd ; Ullrich R. Pfeiffer ; Troy Beukema
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A 0.13-mum SiGe BiCMOS double-conversion superheterodyne receiver and transmitter chipset for data communications in the 60-GHz band is presented. The receiver chip includes an image-reject low-noise amplifier (LNA), RF-to-IF mixer, IF amplifier strip, quadrature IF-to-baseband mixers, phase-locked loop (PLL), and frequency tripler. It achieves a 6-dB noise figure, -30 dBm IIP3, and consumes 500 mW. The transmitter chip includes a power amplifier, image-reject driver, IF-to-RF upmixer, IF amplifier strip, quadrature baseband-to-IF mixers, PLL, and frequency tripler. It achieves output P1dB of 10 to 12dBm, Psat of 15 to 17 dBm, and consumes 800 mW. The chips have been packaged with planar antennas, and a wireless data link at 630 Mb/s over 10 m has been demonstrated

Published in:

IEEE Journal of Solid-State Circuits  (Volume:41 ,  Issue: 12 )