By Topic

A 5-GHz 108-Mb/s 2 \times 2 MIMO Transceiver RFIC With Fully Integrated 20.5-dBm {\rm P}_{\rm 1dB} Power Amplifiers in 90-nm CMOS

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

12 Author(s)

Multiple antenna transceivers combined with MIMO signal processing offer the potential for increased data rates and/or range in wireless systems. This paper presents a fully integrated 5-GHz 2times2 MIMO WLAN transceiver RFIC implemented in 90-nm CMOS. The paper identifies the key MIMO integration issues and proposes techniques to optimize MIMO performance. It is shown that crosstalk between the multiple transceivers residing on the same die can degrade MIMO performance and has to be carefully minimized, especially when power amplifiers are integrated on-die. A shared LO generation and distribution network is designed to maximize MIMO phase noise immunity without introducing undesired crosstalk. The fabricated MIMO receiver achieves a sensitivity of -63 dBm while receiving 108Mb/s in MIMO spatial multiplexing mode in the presence of a 25-ns Rayleigh fading channel. The sensitivity of a single receiver in the presence of AWGN noise is -76 dBm. Linearized 3.3-V 5-GHz power amplifiers with P1dB=20.5<!-- Character "" changed to --> dBm deliver an average power of +13/+16 dBm each, in MIMO/SISO modes respectively (EVM=-27/-25 dB). The measured performance demonstrates the effectiveness of the isolation techniques employed. The system in a package includes an 18 mm2 die and microstrip front-end matching networks implemented on a flip-chip package

Published in:

IEEE Journal of Solid-State Circuits  (Volume:41 ,  Issue: 12 )