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A 9.95–11.3-Gb/s XFP Transceiver in 0.13- \mu{\hbox {m}} CMOS

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14 Author(s)

A 9.95-11.3-Gb/s transceiver in 0.13-mum CMOS for XFP modules is presented. The CDR uses a dual-loop DLL/PLL with a binary phase detector to exceed XFP jitter specifications. The dual loop solves the problem of having a controlled jitter transfer bandwidth with a binary phase detector. A half rate binary phase detector with a 2:1 serializer implements full-rate I/O. Dispersion jitter from 12'' of FR4 is equalized resulting in system JGEN under 4 mUIRMS and 35 mUI PP. Power consumption is 800 mW

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IEEE Journal of Solid-State Circuits  (Volume:41 ,  Issue: 12 )