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A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13- 
CMOS
A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13-
An asynchronous analog-to-digital converter (ADC) based on successive approximation is used to provide a high-speed (600-MS/s) and medium-resolution (6-bit) conversion. A high input bandwidth (>4 GHz) was achieved which allows its use in RF subsampling applications. By using asynchronous processing techniques, it avoids clocks at higher than the sample rate and speeds up a nonbinary successive approximation algorithm utilizing a series nonbinary capacitive ladder with digital radix calibration. The sample rate of 600 MS/s was achieved by time-interleaving two single ADCs, which were fabricated in a 0.13-mum standard digital CMOS process. The ADC achieves a peak SNDR of 34 dB, while only consuming an active area of 0.12mm2 and having power consumption of 5.3 mW
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:41
,
Issue:
12
)
Date of Publication: Dec. 2006
- Page(s):
- 2669 - 2680
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 9193669
- Digital Object Identifier :
- 10.1109/JSSC.2006.884231
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 20 November 2006
- Issue Date :
- Dec. 2006
- Sponsored by :
- IEEE Solid-State Circuits Society
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