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A 0.5-GHz to 2.5-GHz PLL With Fully Differential Supply Regulated Tuning

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4 Author(s)
Brownlee, M. ; Sch. of Electr. Eng. & Comput. Sci., Oregon State Univ., Corvallis, OR ; Hanumolu, P.K. ; Mayaram, K. ; Un-Ku Moon

This paper describes a wide-range clock generation phase-locked loop (PLL) incorporating several features that make it suitable for integration in highly scaled processes. A fully differential supply regulated tuning scheme is used to combat power supply noise. The charge pump uses a resistor rather than an active current source to define the pumping current in order to reduce the charge pump flicker noise. Fabricated in a 0.18-mum CMOS process, the PLL occupies 0.15 mm2 die area and achieves a frequency range of 0.5 to 2.5 GHz. When operating at 2.4 GHz, the power consumption is 14 mA from a 1.8-V supply while the jitter is 2.36 ps rms

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:41 ,  Issue: 12 )