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A Fully Integrated 20-Gb/s Optoelectronic Transceiver Implemented in a Standard 0.13- \mu{\hbox {m}} CMOS SOI Technology

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4 Author(s)

A dual-channel 10 Gb/s per channel single-chip optoelectronic transceiver has been demonstrated in a 0.13-mum CMOS SOI technology. The transceiver integrates conventionally discrete optoelectronic functions such as high-speed 10-Gb/s electro-optic modulation and 10-Gb/s optical reception on an SOI substrate using a standard CMOS process. The high optical index contrast between silicon (n=3.5) and its oxide (n=1.5) allows for very large scale integration of optical devices, while the use of a standard CMOS process allows these devices to be seamlessly fabricated together with electronics on the same substrate. Such a high level of optoelectronic integration is unprecedented, and serves to substantially reduce system footprint and power dissipation, allowing efficient scaling to higher data rates and broader functionality. This paper describes the photonic components, electronic blocks, and architecture of a CMOS photonic transceiver that achieves an aggregate data rate of 20Gb/s in a dual-channel package, with a BER of less than 10-15 and a power consumption of 1.25 W per channel with both channels operating simultaneously

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Solid-State Circuits, IEEE Journal of  (Volume:41 ,  Issue: 12 )