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An Efficient Low-Power Repeater-Insertion Scheme

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2 Author(s)
Yuantao Peng ; Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC ; Xun Liu

Previous repeater-insertion algorithms for power minimization of realistic interconnect trees under given timing budgets are often time consuming. In this paper, the problem of runtime reduction for low-power repeater insertion is investigated. Specifically, a power-sensitivity analysis that links the algorithm runtime and the power dissipation result to the selection of repeater library and candidate repeater locations is performed. Based on the analysis, possible repeater locations and potential repeater widths are selected to increase the efficiency of the low-power repeater-insertion algorithm, achieving a judicious tradeoff between runtime and power savings. Moreover, a novel repeater-insertion algorithm based on the Lagrangian relaxation framework is proposed. The proposed algorithm combines a local optimizer based on the dynamic programming (DP) technique and a fast global search engine using the "ellipsoid method." As a result, the proposed approach is capable of producing high-quality solutions at a very fast speed and without manual tuning of the algorithm parameters. A repeater-insertion tool called Freeze, which uses the proposed algorithm, is developed and applied to various interconnect trees with different timing targets. Experimental results demonstrate the high effectiveness of the proposed approach. In comparison with the state-of-the-art low-power repeater-insertion schemes, Freeze requires 5.8 times fewer iterations on the average, achieving a speedup of up to 9.1 times with even better power savings. When compared with a DP-based scheme, which guarantees the optimal solution, the proposed tool delivers a speedup of up to 14.6 times with less than 2% power increase on the average

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:25 ,  Issue: 12 )