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Reducing Structural Bias in Technology Mapping

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5 Author(s)
Satrajit Chatterjee ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA ; Alan Mishchenko ; Robert K. Brayton ; Xinning Wang
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Technology mapping, based on directed acyclic graph covering, suffers from the problem of structural bias: The structure of the mapped netlist depends strongly on the subject graph. In this paper, the authors present a new mapper aimed at mitigating structural bias. It is based on a simplified cut-based Boolean-matching algorithm, and using the speed afforded by this simplification, they explore two ideas to reduce structural bias. The first, called lossless synthesis, leverages recent advances in structure-based combinational-equivalence checking to combine the different networks seen during technology-independent synthesis into a single network with choices in a scalable manner. They show how cut-based mapping extends naturally to handle such networks with choices. The second idea is to combine several library gates into a single gate (called a supergate) in order to make the matching process less local. They show how supergates help address the structural-bias problem and how they fit naturally into the cut-based Boolean-matching scheme. An implementation based on these ideas significantly outperforms state-of-the-art mappers in terms of delay, area, and run-time on academic and industrial benchmarks

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:25 ,  Issue: 12 )