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Parallel polygon rendering on the graphics computer VC-1

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2 Author(s)
Kunii, T.L. ; Sch. of Comput. Sci. & Eng., Aizu Univ., Japan ; Nishimura, S.

This paper describes a parallel polygon rendering method on the graphics computer VC-1. The architecture of the VC-1 is a loosely-coupled array of general-purpose processors, each of which is equipped with a local frame buffer. The contents of the local frame buffers are merged into one in real time considering the visibility control based on screen depth. In our polygon rendering method, polygons are distributed among the processors and each processor independently computes the image of the assigned polygons using the Z-buffer method. To achieve load balancing, a technique called adaptive parallel rasterization is developed. The adaptive parallel rasterization automatically selects the appropriate parallelizing approach according to the estimated size of polygons displayed on the screen. The measured rendering performance of VC-1 using this polygon rendering method is shown

Published in:

Parallel Algorithms/Architecture Synthesis, 1995. Proceedings., First Aizu International Symposium on

Date of Conference:

15-17 Mar 1995