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Automatic Synthesis of Efficient Intrusion Detection Systems on FPGAs

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2 Author(s)
Baker, Z.K. ; Dept. of Electr. Eng., Southern California Univ., Los Angeles, CA ; Prasanna, V.K.

This paper presents a methodology and a tool for automatic synthesis of highly efficient intrusion detection systems using a high-level, graph-based partitioning methodology and tree-based lookahead architectures. Intrusion detection for network security is a compute-intensive application demanding high system performance. The tools implement and automate a customizable flow for the creation of efficient field programmable gate array (FPGA) architectures using system-level optimizations. Our methodology allows for customized performance through more efficient communication and extensive reuse of hardware components for dramatic increases in area-time performance

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Dependable and Secure Computing, IEEE Transactions on  (Volume:3 ,  Issue: 4 )