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An Analog 2-D DCT Processor

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3 Author(s)
Pankaala, M. ; Dept. of Inf. Technol., Turku Univ. ; Virtanen, K. ; Paasio, A.

This paper presents a simple and low-cost analog architecture for computing 2-D discrete cosine transform (2-D DCT). The proposed circuit is aimed for low-power or very high-speed moderate image quality video compression applications. The design uses current-mode signaling and has two separate 1-D DCT kernels, thus no memory is needed for storing intermediate results. Moreover, the circuit works in continuous time. Simple current mirrors have been used to realize all the needed matrix operations and the transistors are dimensioned in such a way that current level of 20 muA is not exceeded to ensure low-power operation. A prototype chip which includes both 4-point and 8-point forward transforms has been fabricated in a 0.18-mum digital CMOS technology. The operation of the circuit is analyzed with help of measurement results obtained from test chips

Published in:
Circuits and Systems for Video Technology, IEEE Transactions on  (Volume:16 ,  Issue: 10 )

Date of Publication: Oct. 2006

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