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SRAM bitmap shape recognition and sorting using neural networks

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3 Author(s)
Collica, R.S. ; Digital Equipment Corp., Hudson, MA, USA ; Card, J.P. ; Martin, W.

This paper details the use of neural network technologies in the characterization of bit fail patterns occurring on SRAM chips as an alternative to the more traditional rule-based or knowledge-based approach to fail-pattern occurrence and classification analysis. The results of bit fail pattern count analyses are used both for fault analysis post-processing and manufacturing yield improvement methodologies. The move toward neural network implementation comes in response to prohibitively long processing times required for implementation of rule-based algorithms on more complex devices and the added flexibility of a neural network to learn new fail types in a more adaptive mode. An unsupervised approach to fail pattern identification was implemented on a 128 K SRAM chip using a two-layer Kohonen Self Organizing Map for identification and concurrence of bit fail pattern categories within SRAM chips. A second network utilized a multilayer perceptron (MLP) architecture with backpropagation of error for prediction of the number of occurrences per bitmap of each of the 34 previously identified shape types. The MLP used the output of a SOM as its input vector to assist in the feature extraction by shape type. Both trained networks out-performed existing rule-based algorithms both in ability to identify bit fail pattern types, frequency counts, and speed of processing

Published in:

Semiconductor Manufacturing, IEEE Transactions on  (Volume:8 ,  Issue: 3 )

Date of Publication:

Aug 1995

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