By Topic

A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5-V full-swing BiCMOS dynamic logic circuit

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Kuo, J.B. ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Su, K.W. ; Lou, J.H.

The authors present a BiCMOS dynamic multiplier, which is free from race and charge-sharing problems, using Wallace tree reduction architecture and 1.5-V full-swing BiCMOS dynamic logic circuit. Based on a 1-μm BiCMOS technology, a 1.5-V 8×8 multiplier designed, shows a 2.3× improvement in speed as compared to the CMOS static one

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:30 ,  Issue: 8 )