By Topic

Limitation of CMOS supply-voltage scaling by MOSFET threshold-voltage variation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Shih-Wei Sun ; Adv. Products Res. & Dev. Lab., Motorola Inc., Austin, TX, USA ; P. G. Y. Tsui

A fundamental limit of CMOS supply-voltage (Vcc) scaling has been investigated and quantified as a function of the statistical variation of MOSFET threshold-voltage (VT). Based on the data extracted from a sub 0.5 μm logic technology, the variation of ring-oscillator propagation-delay (Td) significantly increases as Vcc is scaled down towards the MOSFET VT. An empirical power-law relationship was then derived to describe the scattering of circuit speed (ΔTpd ) as a function of MOSFET VT variation (ΔVT ) and (Vcc-VT). Agreement between the model and the experimental data was established for Vcc values from 4.0 to 0.9 V. This fundamental limit of CMOS Vcc, scaling poses an additional challenge for the design and manufacturing of high-performance, low-power portable systems and battery-based equipment

Published in:

IEEE Journal of Solid-State Circuits  (Volume:30 ,  Issue: 8 )