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A neuron-MOS neural network using self-learning-compatible synapse circuits

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4 Author(s)
Shibata, T. ; Dept. of Electron. Eng., Tohoku Univ., Sendai, Japan ; Kosaka, H. ; Ishii, H. ; Ohmi, T.

A circuit technology for self-learning neural network hardware has been developed using a high-functionality device called Neuron MOS Transistor (υMOS) as a key circuit element. A υMOS can perform weighted summation of multiple input signals and thresholding all at a single transistor level based on the charge sharing among multiple capacitors. An electronic synapse cell has been constructed with six transistors by merging a floating-gate EEPROM memory cell into a new-concept υMOS differential-source-follower circuitry. The synapse can represent both positive (excitatory) and negative (inhibitory) weights under single VDD power supply and is free from standby power dissipation. An excellent linearity in the weight updating characteristics of the synapse memory has been also established by employing a simple self-feedback regime in each cell circuitry, thus making it fully compatible to the on-chip self-learning architecture of υMOS neural networks. The basic operation of the synapse cell and a υMOS neural network using the synapse has been experimentally verified using test circuits fabricated by a double-polysilicon CMOS process

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Solid-State Circuits, IEEE Journal of  (Volume:30 ,  Issue: 8 )