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Design of monitored self-checking sequential circuits for enhanced fault models

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3 Author(s)
R. A. Parekhji ; Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Bombay, India ; G. Venkatesh ; S. D. Sherlekar

This paper discusses the design of monitored self-checking sequential circuits for the detection of single and multiple unidirectional stuck-at faults, as well as delay faults. It is shown how the monitoring machine approach provides a uniform error detection mechanism for the detection of these faults. Designs based on this method are shown to compare favourably, in terms of hardware overheads and fault coverage, with previous self-checking implementations based on restricted fault models

Published in:

Test Symposium, 1993., Proceedings of the Second Asian

Date of Conference:

16-18 Nov 1993