An algorithm for test generation of combinational circuits - research and implementation for critical path tracing

An algorithm for test pattern generation of combinational logic circuits - critical path tracing is presented in this paper. Differing from other fault oriented test generation algorithms, this algorithm is circuit oriented and generates test pattern from primary outputs towards primary inputs in a circuit. In addition, it does not need fault simulation, i.e., when a test pattern is obtained all the faults detected by this test pattern can be determined simultaneously. Some fundamental conceptions, detailed description of this algorithm are given in this paper. This algorithm has been implemented at a SUN workstation using C language, and some experimental results are offered.<
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