By Topic

An algorithm for test generation of combinational circuits research and implementation for critical path tracing

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
S. Yin ; Inst. of Comput. Technol., Beijing, China ; D. -Z. Wei

An algorithm for test pattern generation of combinational logic circuits - critical path tracing is presented in this paper. Differing from other fault oriented test generation algorithms, this algorithm is circuit oriented and generates test pattern from primary outputs towards primary inputs in a circuit. In addition, it does not need fault simulation, i.e., when a test pattern is obtained all the faults detected by this test pattern can be determined simultaneously. Some fundamental conceptions, detailed description of this algorithm are given in this paper. This algorithm has been implemented at a SUN workstation using C language, and some experimental results are offered

Published in:

Test Symposium, 1993., Proceedings of the Second Asian

Date of Conference:

16-18 Nov 1993