By Topic

A pragmatic test pattern generation system for scan-designed circuits with logic value constraints

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Eun Sei Park ; Electron. & Telecommun. Res. Inst., Taejon, South Korea

In testing for practical logic circuits, there may exist logic value constraints on some part of logic circuits owing to various requirements on design and test. The inefficiency in handling the logic value constraints during the line justification stage of test generation may result in low fault coverage as well as excessive computer time with numerous fruitless searches. This paper presents a logic value system called taboo logic value to represent the logic value constraints and to identify additional logic value constraints using a taboo logic calculus. Also, a test pattern generation algorithm is discussed to show how the taboo logic system can be incorporated into existing test generation algorithms. Finally, experimental results demonstrate the efficiency of the taboo logic values

Published in:

Test Symposium, 1993., Proceedings of the Second Asian

Date of Conference:

16-18 Nov 1993