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Experimental 0.25-μm-gate fully depleted CMOS/SIMOX process using a new two-step LOCOS isolation technique

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4 Author(s)
Ohno, T. ; NTT LSI Labs., Kanagawa, Japan ; Kado, Y. ; Harada, M. ; Tsuchiya, T.

This paper describes the fabrication process of quarter-micrometer-gate fully depleted CMOS/SIMOX devices, which is characterized by a new lateral isolation technique that can easily achieve 30-nm-class surface planarization and 0.2-μm-class isolation with no degradation of device characteristics. The distinctive feature of this isolation technique is to use high-temperature two-step LOCOS oxidation. The CMOS/SIMOX devices have 50-nm-thick body regions and dual N+/P+ poly-Si gates so that they can surely operate in a fully depleted mode. By applying the CMOS/SIMOX process to the fabrication of a CMOS ring oscillator, which is formed on a gate array designed with a 1.2-μm wiring pitch, short delay times of 30 and 45 ps/stage have been achieved at supply voltages of 2 and 1 V, respectively. This result demonstrates that the present process is useful for the fabrication of a high-speed VLSI circuit operated at a low supply voltage below 2 V.

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Electron Devices, IEEE Transactions on  (Volume:42 ,  Issue: 8 )