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Conversion of redundant binary into two's complement representations

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2 Author(s)
Herrfeld, A. ; Inst. fur Periphere Mikroelektronik, Kassel Univ., Germany ; Hentschke, S.

A static CMOS circuit that converts a redundant binary representation into a two's complement representation is presented. The structure and time delay of the resulting logic are identical to a standard carry look-ahead logic for adders. The resulting layout is very regular, has no diffusion gaps and can be expanded to any desired look-ahead length. The circuit can be used for both multiplication and division

Published in:

Electronics Letters  (Volume:31 ,  Issue: 14 )