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Execution behavior analysis and performance improvement in shared-memory architectures

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3 Author(s)
Xiaodong Zhang ; High-Performance Comput. & Software Lab., Texas Univ., San Antonio, TX, USA ; He, K. ; Butchee, G.

Communications latency forms a major obstacle to effective parallel processing. The bottlenecks of interprocessor communication can be caused by characteristics of a particular architecture or a particular application, and especially by the relationship between the two. We believe that efficient parallel processing requires serious attention to this intersection of architecture and application. In this paper we report: our analysis of the execution behavior of three programs from the SPLASH set, using two multiprocessor systems and a simulator; our identification of one program as especially hostile to multiprocessors; and the results of our efforts to improve the performance of that program by applying our detailed knowledge of the relationship between application and architecture

Published in:

Parallel and Distributed Processing, 1993. Proceedings of the Fifth IEEE Symposium on

Date of Conference:

1-4 Dec 1993