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A parallel force direct based VLSI standard cell placement algorithm

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1 Author(s)
E. I. Horvath ; Dept. of Comput. Sci. & Eng., Florida Atlantic Univ., Boca Raton, FL, USA

A new heuristic algorithm is described. It can be used to minimize the weighted wire length in the placement of modules in VLSI chips. A salient feature of PIREN2.0 is that multiple permutations based upon the connectivity between the modules are made simultaneously on all modules in order to minimize the objective function. This allows the algorithm, without major modifications, to be mapped to a processor array structure, the MasPar MP-2.2. Each processor in this massively parallel single instruction, multiple data (SIMD) machine can perform in parallel the computation necessary to place cells in an optimum relative location to one another based upon the connectivity (the number of wires) between cells. A speedup for the benchmark circuits of at least 7.5 is obtained from the parallel version without degrading the quality of the layout solution

Published in:

Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on

Date of Conference:

3-6 May 1993