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Efficient test vectors for ISCAS sequential benchmark circuits

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2 Author(s)
Lee, S.Y. ; Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA ; Saluja, K.K.

The sequential automatic test pattern generation system FASTEST is implemented with new heuristics to produce efficient test vectors for sequential circuits. The efficiency of FASTEST in terms of the quality of test vectors is demonstrated. The test vectors provide excellent fault coverage by fairly short test sequences. The profile of the ISCAS benchmark circuits is also described

Published in:

Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on

Date of Conference:

3-6 May 1993