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Active compensation of parasitic capacitances for very high frequency CMOS DACs

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4 Author(s)
S. Brigati ; Dipartimento di Elettronica, Pavia Univ., Italy ; G. Caiulo ; F. Maloberti ; G. Torelli

High frequency digital-analog (DACs) requiring an output buffer find a speed limitation in the overall input capacitive load of the buffer. An active scheme for the compensation of such a load, including the parasitic capacitances coming from reversely biased junctions associated with analog switches is presented. Computer simulations on a given architecture (10-b DAC) show the effectiveness of the proposed approach

Published in:

Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on

Date of Conference:

3-6 May 1993