An intelligent I-cache prefetch mechanism

Modern, high-performance processors employ techniques such as superscalar execution and super-pipelining to increase their instruction issue rate. As the instruction issue rate of processors increases, however, the negative impact of branches on performance also increases. This paper describes an instruction cache (I-cache) prefetch mechanism to improve processor performance on the taken branches. Under perfect conditions, the mechanism allows the target of a taken branch to be prefetched early enough to completely hide the memory latency of an I-cache miss.<
>