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Towards a methodology for the formal hierarchical verification of RISC processors

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2 Author(s)
Tahar, S. ; Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany ; Kumar, R.

A general methodology, based on a hierarchical model of interpreters, is presented for formally verifying RISC cores. The abstraction levels used by a designer in the implementation of RISC cores, namely the instruction set level, the pipeline stage level, the phase level and the hardware implementation, are mirrored by this hierarchical model. The use of this model allows us to successively prove the correctness between two neighboring levels of abstractions, so that the verification process is simplified. The parallelism in the execution of the instructions, resulting from the pipelined architecture of RISCs is handled by splitting the proof into simplified steps. The first step shows that, under certain assumptions, no conflicts can occur between simultaneously executed instructions, and the second step shows that each instruction is implemented correctly by the sequential execution of its pipeline steps

Published in:

Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on

Date of Conference:

3-6 Oct 1993