A path sensitization approach to area reduction

We study the problem of choosing gate implementations to reduce circuit area while retaining the circuit performance. To incorporate timing analysis into area reduction, we propose to utilize the information provided by a sensitization criterion in computing the slacks of the gates. Not all sensitization criteria can be adopted in our approach. Some conditions were imposed to define a class of sensitization criteria which can guarantee that the circuit performance will be preserved. A greedy area reduction heuristic is proposed, and then an improved version of the Brand-Iyengar and the static sensitization criteria are plugged into the heuristic to obtain results for comparison (D. Brand, V. Iyengar, 1986).<
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