By Topic

Determining cost-effective multiple issue processor designs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Conte, T.M. ; Dept. of Electr. & Comput. Eng., South Carolina Univ., Columbia, SC, USA ; Mangione-Smith, W.

Several commercial processors, including the Motorola 88110 and the DEC Alpha, are capable of issuing multiple operations per clock cycle. Optimization of the pipeline depth and number of function units in these processors has been largely ignored due to limited semiconductor resources. Recently, advances in feature size and packaging technologies have removed these limitations. It is possible that next-generation processor designs may benefit from multiple function unit copies and optimize pipeline depths. The paper investigates the feasibility of performing synthesis at the architectural specification level. The design space is optimized for performance constrained by a hardware model of silicon area. The results of this study indicate that cost-effective high performance can be achieved with the addition of small amounts of function unit duplication. These results are also used to comment on the validity of the “benchmark suite” approach to performance evaluation and machine design

Published in:

Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on

Date of Conference:

3-6 Oct 1993