By Topic

A comparison of synchronous and asynchronous FSMD designs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
R. Auletta ; Dept. of Electr. & Comput. Eng., George Mason Univ., Fairfax, VA, USA ; B. Reese ; C. Traver

This paper presents a comparison of asynchronous and synchronous standard cell implementations for finite state machine with data-path (FSMD) ASICs. The comparison is made through independent parallel designs of a 16-bit factoring ASIC. A common functional specification, standard cell library, and suite of EDA tools for layout and simulation are used to provide a common basis for comparison. To clarify design goals and provide more data for comparison each design is separately optimized for speed and for area. Timing and area information for each design is tabulated and discussed to illustrate the specific advantages and disadvantages of each approach

Published in:

Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on

Date of Conference:

3-6 Oct 1993