By Topic

SMAC: A scene matching chip

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
N. Ranganathan ; Center for Microelectron. Res., South Florida Univ., Tampa, FL, USA ; R. Sastry ; R. Venkatesan ; J. W. Yoder
more authors

Scene matching is the problem of matching regions of two images of the same scene taken by different sensors at different times or under different viewing conditions. Hierarchical scene matching is a technique for reducing the amount of computation involved in scene matching applications. Most of the past research on this problem has concentrated on efficient software algorithms, and very little effort has been expended on custom hardware solutions. We describe the design of SMAC, a new VLSI architecture for Hierarchical Scene Matching. This architecture achieves a significant amount of speedup by utilizing a large amount of parallelism and pipelining. The paper also describes the design and implementation of a prototype CMOS VLSI chip that implements the exhaustive search task of the scene matching algorithm

Published in:

Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on

Date of Conference:

3-6 Oct 1993