By Topic

Hardware self-tuning and circuit performance monitoring

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
T. Kehl ; Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA

Self-tuning is a new clocking methodology borrowing heavily from both the synchronous and self-timed disciplines. A self-tuned system has an adjustable clock and measurement logic. During the tuning process the adjustable clock is made to run faster and faster until before the system fails. After tuning and during operation each cycle is measured and, if a failure is imminent, the system is retuned. During the tuning phase test vectors-either hardware embedded or software-select near maximum speed for a particular instance of the system. As self-tuning is predicated on self-test, it is essential to build in self-test features. These same self-test features are useful in circuit level performance monitoring. Two extremes on the continuum of self-tuning are discussed: at one extreme is purely hardware self-tuning and at the other, nearly purely software. Data is given from an experimental self-tuned primary memory indicating 70 ns access time DRAM can be operated at 45 ns or less

Published in:

Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on

Date of Conference:

3-6 Oct 1993