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A 8.8-ns 54×54-bit multiplier using new redundant binary architecture

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3 Author(s)
Makino, H. ; Mitsubishi Electr. Corp., Mizuhara, Itami, Japan ; Nakase, Y. ; Shinohara, H.

A new redundant binary (RB) architecture for a high-speed multiplier is presented. In this architecture, a pair of partial products is converted to one RB number by inverting one of the pair without additional circuitry or latency. Generated RB partial products are added by the Wallace tree of improved RB adders (RBAs) which have a latency of 0.9 ns, and converted to a normal binary (NB) number by a simply structured RB-to-NB converter in which the carry-propagation circuit is constructed only with simple selector circuits. A 54×54-bit multiplier is designed using 0.5-μm CMOS technology. A multiplication time of 8.8 ns is obtained by SPICE2 simulation for a supply voltage of 3.3 V which is the fastest that has been reported for 54×54-bit multipliers

Published in:

Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on

Date of Conference:

3-6 Oct 1993