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A new high performance field programmable gate array family

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2 Author(s)
Whitney, T. ; Actel Corp., Sunnyvale, CA, USA ; Schlageter, J.

Describes a 0.8 μm FPGA CMOS family that closes the speed gap between masked programmable gate arrays and FPGAs. This architecture achieves 16-bit counter speeds of 125 MHz and 65 MHz general system performance. The Act3 architecture includes a new more flexible I/O module and two fast clocks allowing clock-to-out speeds of 10 ns. The logic module is based on the Act2 logic module, but is more uniform and thus more amenable to synthesis. This family includes parts ranging from 1500 gates to 10,000 gates. The use of a chip compiler allows rapid generation of the entire family. The key to the generation of the designs was a compact layout and schematic tile set used for the entire family, with personalization handled by the compiler

Published in:

Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on

Date of Conference:

3-6 Oct 1993