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Channel architecture optimization for performance and routability of row-based FPGAs

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3 Author(s)
Roy, K. ; Texas Instrum., Dallas, TX, USA ; Nag, S. ; Dutta, S.

Considers routability and performance-driven optimization of a segmented channel architecture for row-based field programmable gate arrays (FPGAs). The routability of a channel and the performance of the routed circuit may have conflicting requirements. For a given number of tracks, very short segments usually enhance routability at the expense of performance. A simulated annealing-based channel segmentation optimization scheme has been developed, which enhances channel routability and performance based on the correlation between segment and net distributions. Excellent results have been obtained for a set of benchmark examples and industrial designs

Published in:

Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on

Date of Conference:

3-6 Oct 1993