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A reconfiguration-based yield enhancement system

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2 Author(s)
Narasimhan, J. ; IBM T.J. Watson Res. Center, Yorktown Heights, NY, USA ; Nakajima, K.

An approach to yield enhancement of programmable array chips by logical restructuring of circuit placements was recently proposed by Kumar et al. (1991). and a graph model for its reconfiguration aspect was later introduced by Narasimhan et al. (1991). Using this model and a new cost measure, we present a complete yield enhancement system. We implement two reconfiguration algorithms on it, evaluate their performances, and propose good reconfiguration strategies

Published in:

Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on

Date of Conference:

3-6 Oct 1993