By Topic

Synthesis of controllers from interval temporal logic specification

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
M. Fujita ; Fujitsu Lab. Ltd., Kawasaki, Japan ; S. Kono

Presents a method which accepts interval temporal logic (ITL) formulas as a specification and automatically generates state machines. The specification in ITL can also be used as a constraint for a state machine that is an abstraction for an existing sequential circuit, which can be useful for redesign or engineering change. The generated state machines can be further processed by a logic synthesizer, such as SIS. We present experimental results and show the usefulness of our method

Published in:

Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on

Date of Conference:

3-6 Oct 1993