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Synthesis of controllers from interval temporal logic specification

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2 Author(s)
Fujita, M. ; Fujitsu Lab. Ltd., Kawasaki, Japan ; Kono, S.

Presents a method which accepts interval temporal logic (ITL) formulas as a specification and automatically generates state machines. The specification in ITL can also be used as a constraint for a state machine that is an abstraction for an existing sequential circuit, which can be useful for redesign or engineering change. The generated state machines can be further processed by a logic synthesizer, such as SIS. We present experimental results and show the usefulness of our method

Published in:

Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on

Date of Conference:

3-6 Oct 1993

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