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A systolic architecture for high speed pipelined memories

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2 Author(s)
A. G. Dickinson ; AT&T Bell Lab., Holmdel, NJ, USA ; C. J. Nicol

Proposes a scalable memory architecture that maintains a high data rate, independent of address sequence and memory size. It is suitable for applications where throughput is of primary importance and access latency is tolerable. A rectangular array of memory blocks is pipelined to build a memory with an operating frequency determined only by the access time of a single block. This is independent of the number of blocks because address and data communication is localized to adjacent memory blocks. Rather than sacrificing speed for memory size, the new approach scales to provide high-throughput random access memories of very large size with some increase in latency

Published in:

Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on

Date of Conference:

3-6 Oct 1993