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Pica: An ultra-light processor for high-throughput applications

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6 Author(s)
Wills, D.S. ; Sch. of Electr. Eng., Georgia Inst. of Technol., Atlanta, GA, USA ; Lacy, W.S. ; Cat, H. ; Hopper, M.
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Introduces Pica, a fine-grain, message-passing architecture designed to efficiently support high-throughput parallel applications. The architecture minimizes overhead for basic parallel operations. An operand-addressed context cache and round-robin task manager allow single-cycle task swaps. Fixed-sized activation contexts simplify storage management. Word-tag synchronization bits provide low-cost synchronization. The focus on high-throughput applications allows a small local memory (1024 36-bit words). A complete node (including memory) can be implemented using a fraction of a chip. A multi-node chip prototype (four nodes/chip) is being designed. In order to meet chip I/O requirements, a high-bandwidth 3D optical network is also being designed. Using recent developments in epitaxial liftoff of optoelectronic devices and through-chip transmission, a network is presented that provides 3.2 Gbit/s off-chip bandwidth

Published in:

Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on

Date of Conference:

3-6 Oct 1993