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Logic optimization with multi-output gates

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3 Author(s)
Watanabe, Y. ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; Guerra, L. ; Brayton, R.K.

This paper is concerned with logic optimization of multi-output gates in multi-level combinational logic circuits. We address how a concurrent minimization over multiple gates can lead to further optimization as compared to conventional single-gate minimization techniques. In particular, we provide a procedure for computing a maximally-compatible set of permissible relations for multiple-output gates. We also propose a heuristic for clustering single-output gates into multi-output gates, so that increased concurrent optimization can be obtained

Published in:

Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on

Date of Conference:

3-6 Oct 1993

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