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Physically realizable gate models

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2 Author(s)
Stephan, P.R. ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; Brayton, R.K.

Proposes an objective criterion for determining if, given a specific circuit technology, a gate model is suitable for synthesis and verification. This is based on relating the analog circuit behavior to the digital model behavior using a formal definition of implementation. We illustrate the type of design errors which occur when the criterion is not satisfied, and introduce a gate model designed to satisfy the criterion

Published in:

Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on

Date of Conference:

3-6 Oct 1993