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Beyond superscalar using FPGAs

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2 Author(s)
C. Iseli ; Logic Syst. Lab., Swiss Federal Inst. of Technol., Lausanne, Switzerland ; E. Sanchez

A superscalar processor with three execution units is described in details in this paper. The execution units are implemented using reprogrammable field-programmable gate array (FPGA) chips, allowing the user to configure them to best fit the application. Each instruction, composed of 128 bits, directly controls all the processor resources, in a horizontal microprogramming way

Published in:

Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on

Date of Conference:

3-6 Oct 1993