By Topic

Design for testability of asynchronous sequential circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Saxena, J. ; Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA ; Pradhan, D.K.

Asynchronous sequential circuits are becoming increasingly important with their potential for higher speed and as clock skew problems in synchronous circuits continue to persist. Modifications to asynchronous machines that will allow ease of testability are presented in this paper. The framework of checking experiments is used for evaluating the proposed design. Checking experiments, though complex, can provide a methodology for complete functional testing as well as design verification. The design techniques proposed here can be adapted for testing under the traditional stuck-at fault model as well

Published in:

Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on

Date of Conference:

3-6 Oct 1993