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A logic-level model for α-particle hits in CMOS circuits

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2 Author(s)
Hungse Cha ; Center for Reliable & High-Performance Comput., Illinois Univ., Urbana, IL, USA ; Patel, J.H.

Systems designed for reliability must be validated through simulations. However, traditional SPICE like simulators or even mixed-mode simulators are too slow for the task of simulating the effects of α-particle hits on relatively large circuits. Gate-level simulators offer tremendous speedup over these electrical level simulators, but they are only as good as the model which captures the α-particle effect at the logic level. The goal of this research is to develop a computationally efficient model which captures the behavior of the α-particle at the logic level. This model can then be used in a gate-level timing simulator to propagate the α-particle effects to the latches and the outputs of the circuit under simulation. We have developed a closed form solution to approximate the logic pulse waveform resulting from α-particle hits. As is presented in the paper, the model tracks the data from SPICE simulations remarkably well

Published in:

Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on

Date of Conference:

3-6 Oct 1993