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Pipelined fault simulation on parallel machines using the circuit flow graph

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2 Author(s)
Tai, S.-E. ; AT&T Bell Lab., Allentown, PA, USA ; Bhattacharya, D.

A new technique to parallelize fault simulation for combinational digital circuits, suitable for message passing based parallel processors, is described. Speedup is achieved via combined use of data flow analysis and pipeline-like communication between processors. Unlike previous algorithms based on fault partitioning only, this approach uses both circuit and fault partitioning, and is both memory- and time-efficient with increasing number of processors

Published in:

Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on

Date of Conference:

3-6 Oct 1993