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Functional fault models and gate level coverage for sequential architectures

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3 Author(s)
Buonanno, G. ; Dipartimento di Elettronica, Politecnico di Milano, Italy ; Fummi, F. ; Sciuto, D.

This paper introduces and evaluates functional fault models for test pattern generation of sequential circuits at the finite state machine level. Evaluation of the proposed fault models against their gate level fault coverage on multi-level implementations is presented. The relationships between functional and gate level fault coverage are discussed

Published in:

Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on

Date of Conference:

3-6 Oct 1993

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