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A new modulo 2a+1 multiplier

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2 Author(s)
Wrzyszcz, A. ; Dept. of Electr. & Electron. Eng., Bristol Univ., UK ; Milford, D.

This paper presents the design of a new modulo 2a + 1 multiplier. It makes use of the redundancy in the binary representation of numbers in the finite integer ring R(21+1), though, unlike in some other designs, code translations are not involved. The use of the periodic properties of powers of two taken modulo 2a+1 simplifies the result correction process and permits a highly regular circuit structure which is suitable for VLSI implementation. Since the multiplier is almost exclusively composed of full and half adders, it can easily be pipelined with throughput reaching hundreds of megahertz. Such performance should make the implementation very attractive in many DSP applications

Published in:

Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on

Date of Conference:

3-6 Oct 1993