By Topic

1.1 V high speed, low power BiCMOS logic circuit

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Yeo Kiat Seng ; Sch. of Electr. & Electron. Eng., Nanyang Technol. Inst., Singapore ; Rofail, S.S.

A 1.1 V full switching high speed, low power BiCMOS logic circuit is presented. It consists of nine devices and uses a noncomplementary BiCMOS process. Bootstrapping and partial charge removal techniques are employed. HSPICE simulations have shown that the new circuit outperforms both CMOS and a recently reported circuit in terms of speed and power-delay product. An analytical expression relating the pull-up delay with its device parameters is also derived

Published in:

Electronics Letters  (Volume:31 ,  Issue: 13 )