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A 1.5 GHz highly linear CMOS downconversion mixer

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2 Author(s)
J. Crols ; ESAT-MICAS, Katholieke Univ., Leuven, Heverlee, Belgium ; M. S. J. Steyaert

A CMOS mixer topology for use in highly integrated downconversion receivers is presented. The mixing is based on the modulation of nMOS transistors in the triode region which renders an excellent linearity independent of mismatch. With two extra capacitors added to the classical cross-coupled MOSFET-C lowpass filter structure, GHz signals can be processed while only a low-frequency opamp is required as output amplifier. The downconversion mixer has an input bandwidth of 1.5 GHz. The measured third-order intercept point (IP3) of 45.2 dBm demonstrates the high linearity. The mixer has been implemented in a 1.2 μm CMOS process. It takes up 1 mm2 of total chip area and its power consumption is 1.3 mW from a single 5 V power supply

Published in:

IEEE Journal of Solid-State Circuits  (Volume:30 ,  Issue: 7 )